#include "PCFuncTestSimd.h"
#include <stdio.h>
#include "PCFuncSimd.h"
#include "common.h"
#include <string.h>
#include "float_def.h"
#include <math.h>

FILE *simd_mem_upasm_file, *simd_upinc_file, *simd_upasm_file;

U31CodeFile simd_code_file;

Reg32 f_a[] = {
    f_qnan,            // 0xFFC00000  //1 11111111 10000000000000000000000 qnan 安静nann
    f_snan,            // 0xFF800001  //1 11111111 00000000000000000000001 snan 信号nan
    f_infinity_n,      // 0xFF800000  //1 11111111 00000000000000000000000 -inf 负无穷大
    f_infinity,        // 0x7F800000  //0 11111111 00000000000000000000000 +inf 正无穷大
    f_0,               // 0x00000000  //0 00000000 00000000000000000000000 0.000000000  正0
    f_0_n,             // 0x80000000  //1 00000000 00000000000000000000000 -0.000000000 负0
    f_max_normal,      // 0x7F7FFFFF  //0 11111110 11111111111111111111111  3.4028235e+38 最大的规格数
    f_max_normal_n,    // 0xFF7FFFFF  //1 11111110 11111111111111111111111 -3.4028235e+38 最大的规格数的相反数
    f_min_normal,      // 0x00800000  //0 00000001 00000000000000000000000  1.1754942e-38 最小的规格数
    f_min_normal_n,    // 0x80800000  //1 00000001 00000000000000000000000 -1.1754942e-38 最小的规格数的相反数
    f_max_subnormal,   // 0x007FFFFF  //0 00000000 11111111111111111111111 最大的非规格数
    f_max_subnormal_n, // 0x807FFFFF  //1 00000000 11111111111111111111111 最大的非规格数的相反数
    f_min_subnormal,   // 0x00000001  //0 00000000 00000000000000000000001  1.4012985e-45 最小的非规格数
    f_min_subnormal_n, // 0x80000001  //1 00000000 00000000000000000000001 -1.4012985e-45 最小的非规格数的相反数
    f_1,               // 0x3F800000  //0 01111111 00000000000000000000000  1.0000000e+00 整数1
    f_1_n,             // 0xBF800000  //1 01111111 00000000000000000000000 -1.0000000e+00 整数1的相反数
    f_acc_1,           // 0x4B800000  //0 10010111 00000000000000000000000  1.6777216e+07 精度1.0f的数
    f_acc_1_n,         // 0xCB800000  //1 10010111 00000000000000000000000 -1.6777216e+07 精度1.0f的数的相反数
    f_pi,              // 0x40490FDB  //0 10000000 10010010000111111011011  3.1415927410125732 圆周率
    f_pi_n,            // 0xC0490FDB  //1 10000000 10010010000111111011011 -3.1415927410125732 圆周率的相反数
    f_sqrt2,           // 0x3FB504F3  //0 01111111 01101010000010011110011  1.4142135381698608 根号2
    f_sqrt2_n,         // 0xBFB504F3  //1 01111111 01101010000010011110011 -1.4142135381698608 根号2的相反数
    f_sqrt3,           // 0x3FDDB3D7  //0 01111111 10111011011001111010111  1.7320507764816284 根号3
    f_sqrt3_n,         // 0xBFDDB3D7  //1 01111111 10111011011001111010111 -1.7320507764816284 根号3的相反数
    f_e,               // 0x402DF854  //0 10000000 01011011111100001010100  2.7182817459106445 自然底数e
    f_e_n,             // 0xC02DF854  //1 10000000 01011011111100001010100 -2.7182817459106445 自然底数e的相反数
};

Reg32 f_b[] = {
    f_qnan,            // 0xFFC00000  //1 11111111 10000000000000000000000 qnan 安静nann
    f_snan,            // 0xFF800001  //1 11111111 00000000000000000000001 snan 信号nan
    f_infinity_n,      // 0xFF800000  //1 11111111 00000000000000000000000 -inf 负无穷大
    f_infinity,        // 0x7F800000  //0 11111111 00000000000000000000000 +inf 正无穷大
    f_0,               // 0x00000000  //0 00000000 00000000000000000000000 0.000000000  正0
    f_0_n,             // 0x80000000  //1 00000000 00000000000000000000000 -0.000000000 负0
    f_max_normal,      // 0x7F7FFFFF  //0 11111110 11111111111111111111111  3.4028235e+38 最大的规格数
    f_max_normal_n,    // 0xFF7FFFFF  //1 11111110 11111111111111111111111 -3.4028235e+38 最大的规格数的相反数
    f_min_normal,      // 0x00800000  //0 00000001 00000000000000000000000  1.1754942e-38 最小的规格数
    f_min_normal_n,    // 0x80800000  //1 00000001 00000000000000000000000 -1.1754942e-38 最小的规格数的相反数
    f_max_subnormal,   // 0x007FFFFF  //0 00000000 11111111111111111111111 最大的非规格数
    f_max_subnormal_n, // 0x807FFFFF  //1 00000000 11111111111111111111111 最大的非规格数的相反数
    f_min_subnormal,   // 0x00000001  //0 00000000 00000000000000000000001  1.4012985e-45 最小的非规格数
    f_min_subnormal_n, // 0x80000001  //1 00000000 00000000000000000000001 -1.4012985e-45 最小的非规格数的相反数
    f_1,               // 0x3F800000  //0 01111111 00000000000000000000000  1.0000000e+00 整数1
    f_1_n,             // 0xBF800000  //1 01111111 00000000000000000000000 -1.0000000e+00 整数1的相反数
    f_acc_1,           // 0x4B800000  //0 10010111 00000000000000000000000  1.6777216e+07 精度1.0f的数
    f_acc_1_n,         // 0xCB800000  //1 10010111 00000000000000000000000 -1.6777216e+07 精度1.0f的数的相反数
    f_pi,              // 0x40490FDB  //0 10000000 10010010000111111011011  3.1415927410125732 圆周率
    f_pi_n,            // 0xC0490FDB  //1 10000000 10010010000111111011011 -3.1415927410125732 圆周率的相反数
    f_sqrt2,           // 0x3FB504F3  //0 01111111 01101010000010011110011  1.4142135381698608 根号2
    f_sqrt2_n,         // 0xBFB504F3  //1 01111111 01101010000010011110011 -1.4142135381698608 根号2的相反数
    f_sqrt3,           // 0x3FDDB3D7  //0 01111111 10111011011001111010111  1.7320507764816284 根号3
    f_sqrt3_n,         // 0xBFDDB3D7  //1 01111111 10111011011001111010111 -1.7320507764816284 根号3的相反数
    f_e,               // 0x402DF854  //0 10000000 01011011111100001010100  2.7182817459106445 自然底数e
    f_e_n,             // 0xC02DF854  //1 10000000 01011011111100001010100 -2.7182817459106445 自然底数e的相反数
};

void test()
{
    Reg32 b[10] = {0}; // 测试10组随机顺序
    Reg64 opt2 = {0};
    Reg64 tmp = {0};
    for (size_t i = 0; i < 10 / 2; i++)
    {
        random64(&tmp);
        b[2 * i].word = tmp.word[0];
        b[2 * i + 1].word = tmp.word[1];
        for (size_t i = 0; i < 2; i++)
        {
            printf(" 0x%08x ", tmp.word[i]);
        }
    }
    Reg32 f1 = {0};
    Reg32 f2 = {0};
    Reg32 res = {0};

    // f1.f = 1.3333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333;
    // f2.f = 3.0;

    f1.word = 0x1c800000;
    f2.word = 0x1c8fe000;
    res.f = f1.f * f2.f;
    printf("\n---------------------\n");

    printf(" 0x%08x %lf", res.word, res.f);
}

void test_simd_match8()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg32 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_match8);
}
void test_simd_unpack8()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg64 opt1 = {0};
    Reg64 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_unpack8);
}
void test_simd_unpack16()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg64 opt1 = {0};
    Reg64 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_unpack16);
}
void test_simd_add8_ext1()
{
    Reg32 a[] = {0x7fffffff, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg32 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_add8_ext1);
}
void test_simd_sub8_ext1()
{
    Reg32 a[] = {0x7fffffff, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg32 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_sub8_ext1);
}
void test_simd_add8_ext2()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg32 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_add8_ext2);
}
void test_simd_sub8_ext2()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg32 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_sub8_ext2);
}
void test_simd_add16_ext1()
{
    Reg32 a[] = {0x7fffffff, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg32 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_add16_ext1);
}
void test_simd_sub16_ext1()
{
    Reg32 a[] = {0x7fffffff, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg32 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_sub16_ext1);
}
void test_simd_add16_ext2()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg32 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_add16_ext2);
}
void test_simd_sub16_ext2()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg32 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_sub16_ext2);
}
void test_simd_mask8()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg32 dst = {0};

    GENERATE_1_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, opt1, dst, simd_mask8);
}
void test_simd_mask16()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg32 dst = {0};

    GENERATE_1_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, opt1, dst, simd_mask16);
}

void test_simd_match16()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg32 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_match16);
}
void test_simd_shuffle8()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[10] = {0}; // 测试5组随机顺序

    Reg128 opt1 = {0};
    Reg64 opt2 = {0};
    Reg128 dst = {0};
    Reg64 tmp = {0};
    for (size_t i = 0; i < 10 / 2; i++)
    {
        random64(&tmp);
        b[2 * i].word = tmp.word[0];
        b[2 * i + 1].word = tmp.word[1];
    }
    // GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_shuffle8);
    char arr[] = "simd_shuffle8";

    size_t a_size = sizeof(a) / sizeof(U32);
    size_t b_size = sizeof(b) / sizeof(U32);
    size_t opt1_size = sizeof(opt1) / sizeof(U32);
    size_t opt2_size = sizeof(opt2) / sizeof(U32);
    size_t dst_size = sizeof(dst) / sizeof(U32);
    size_t res_size = a_size * b_size / 2 * dst_size;
    Reg32 res[res_size] = {0};
    size_t index = 0;
    for (size_t i = 0; i < a_size; i++)
    {
        set_opt((void *)&opt1, opt1_size, a, a_size, i);
        for (size_t j = 0; j < b_size / 2; j++)
        {
            memset((char *)&dst, 0x00, sizeof(dst));
            for (size_t i = 0; i < opt2_size; i++)
            {
                opt2.word[i] = b[2 * j + i].word;
            }
            simd_shuffle8(&dst, &opt1, &opt2);
            set_result((Reg32 *)&res, res_size, &index, (void *)&dst, dst_size);
        }
    }
    gen_memupasm_input_data_lable(simd_mem_upasm_file, arr, 1, a, a_size, opt1_size);
    gen_memupasm_input_data_lable(simd_mem_upasm_file, arr, 2, b, b_size, 1);
    gen_mem_upasm_result_data_lable(simd_mem_upasm_file, arr, res, res_size);
    gen_upinc_input_data_lable(simd_upinc_file, arr, 1);
    gen_upinc_input_data_lable(simd_upinc_file, arr, 2);
    gen_upinc_result_data_lable(simd_upinc_file, arr);
    gen_upasm_2_op_code(simd_upasm_file, arr, opt1_size, a_size, opt2_size, b_size / 2, dst_size);
}
void test_simd_8to16()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg64 opt1 = {0};
    Reg128 dst = {0};

    GENERATE_1_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, opt1, dst, simd_8to16);
}
void test_simd_8to32()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 opt1 = {0};
    Reg128 dst = {0};

    GENERATE_1_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, opt1, dst, simd_8to32);
}
void test_simd_16to32()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg64 opt1 = {0};
    Reg128 dst = {0};

    GENERATE_1_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, opt1, dst, simd_16to32);
}
void test_simd_sub16()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_sub16);
}
void test_simd_shift32()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0xffff0000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[32] = {0};

    Reg128 opt1 = {0};
    Reg32 opt2 = {0};
    Reg128 dst = {0};

    size_t b_size = sizeof(b) / sizeof(Reg32);
    Reg32 start = {0};
    start.sword = -16;
    gen_array(b, b_size, start, 1);

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_shift32);
}
void test_simd_shift16()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[31] = {0};

    Reg128 opt1 = {0};
    Reg32 opt2 = {0};
    Reg128 dst = {0};
    size_t b_size = sizeof(b) / sizeof(Reg32);

    Reg32 start = {0};
    start.sword = -15;
    gen_array(b, b_size, start, 1);

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_shift16);
}
void test_simd_add8()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_add8);
}
void test_simd_add8_16()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg64 opt1 = {0};
    Reg64 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_add8_16);
}
void test_simd_max32()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_max32);
}
void test_simd_min32()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_min32);
}
void test_simd_max32_mak()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_max32_mak);
}
void test_simd_min32_mak()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_min32_mak);
}
void test_simd_min16_mak()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_min16_mak);
}
void test_simd_max8_mak()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_max8_mak);
}
void test_simd_min8_mak()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_min8_mak);
}
void test_simd_enlarg8()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg64 opt1 = {0};
    Reg128 dst = {0};

    GENERATE_1_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, opt1, dst, simd_enlarg8);
}
void test_simd_enlarg16()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg64 opt1 = {0};
    Reg128 dst = {0};

    GENERATE_1_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, opt1, dst, simd_enlarg16);
}
void test_simd_enlarg32()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg64 opt1 = {0};
    Reg128 dst = {0};

    GENERATE_1_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, opt1, dst, simd_enlarg32);
}
void test_simd_ext8()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x00000000, 0x00000001};

    Reg32 opt1 = {0};
    Reg32 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_ext8);
}
void test_simd_ext16()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x00000000, 0x00000001};

    Reg32 opt1 = {0};
    Reg32 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_ext16);
}
void test_simd_ext32()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg32 opt1 = {0};
    Reg128 dst = {0};

    GENERATE_1_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, opt1, dst, simd_ext32);
}
void test_simd_set()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg32 opt1 = {0};
    Reg128 dst = {0};

    GENERATE_1_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, opt1, dst, simd_set);
}

void test_simd_mul()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_mul);
}

void test_simd_mac16_8()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 c[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg32 dst = {0};

    GENERATE_2_OP_INIT_DST_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, c, opt1, opt2, dst, simd_mac16_8);
}
void test_simd_fadd()
{
    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, f_a, f_b, opt1, opt2, dst, simd_fadd);
}
void test_simd_fsub()
{
    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, f_a, f_b, opt1, opt2, dst, simd_fsub);
}

void test_simd_fsum()
{
    Reg128 opt1 = {0};
    Reg32 dst = {0};

    GENERATE_1_OP_INIT_DST_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, f_a, f_b, opt1, dst, simd_fsum);
}
void test_simd_fmax1()
{
    Reg128 opt1 = {0};
    Reg32 dst = {0};

    GENERATE_1_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, f_a, opt1, dst, simd_fmax1);
}
void test_simd_fmin1()
{
    Reg128 opt1 = {0};
    Reg32 dst = {0};

    GENERATE_1_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, f_a, opt1, dst, simd_fmin1);
}

void test_simd_fmax4()
{
    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, f_a, f_b, opt1, opt2, dst, simd_fmax4);
}
void test_simd_fmin4()
{
    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, f_a, f_b, opt1, opt2, dst, simd_fmin4);
}
void test_simd_fabs()
{
    Reg128 opt1 = {0};
    Reg128 dst = {0};

    GENERATE_1_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, f_a, opt1, dst, simd_fabs);
}
void test_simd_fmul()
{
    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, f_a, f_b, opt1, opt2, dst, simd_fmul);
}
void test_simd_fmac_4()
{
    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg32 dst = {0};

    GENERATE_2_OP_INIT_DST_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, f_a, f_b, f_b, opt1, opt2, dst, simd_fmac_4);
}
void test_simd_match()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 c[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg32 dst = {0};

    GENERATE_2_OP_INIT_DST_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, c, opt1, opt2, dst, simd_match);
}
void test_simd_16to8()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[8] = {0};

    Reg128 opt1 = {0};
    Reg32 opt2 = {0};
    Reg64 dst = {0};

    size_t b_size = sizeof(b) / sizeof(Reg32);
    Reg32 start = {0};
    start.sword = 0;
    gen_array(b, b_size, start, 1);

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_16to8);
}

void test_simd_32to16()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0, 1};

    Reg128 opt1 = {0};
    Reg32 opt2 = {0};
    Reg64 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_32to16);
}

void test_simd_i8f32()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[8] = {0};

    Reg32 start;
    start.word = 0;

    size_t b_size = sizeof(b) / sizeof(U32);

    gen_array(b, b_size, start, 1);

    Reg32 opt1 = {0};
    Reg32 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_i8f32);
}

void test_simd_i32f32()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[32] = {0};

    Reg32 start;
    start.word = 0;

    size_t b_size = sizeof(b) / sizeof(U32);

    gen_array(b, b_size, start, 1);

    Reg128 opt1 = {0};
    Reg32 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_i32f32);
}

void test_simd_f32i32()
{
    Reg32 b[32] = {0};

    Reg32 start;
    start.word = 0;

    size_t b_size = sizeof(b) / sizeof(U32);

    gen_array(b, b_size, start, 1);

    Reg128 opt1 = {0};
    Reg32 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, f_a, b, opt1, opt2, dst, simd_f32i32);
}
void test_simd_f32i64()
{
    Reg32 b[64] = {0};

    Reg32 start;
    start.word = 0;

    size_t b_size = sizeof(b) / sizeof(U32);

    gen_array(b, b_size, start, 1);

    Reg64 opt1 = {0};
    Reg32 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, f_a, b, opt1, opt2, dst, simd_f32i64);
}
void test_simd_muls16()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg64 opt1 = {0};
    Reg64 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_muls16);
}
void test_simd_mac16_4()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 c[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg64 opt1 = {0};
    Reg64 opt2 = {0};
    Reg32 dst = {0};

    GENERATE_2_OP_INIT_DST_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, c, opt1, opt2, dst, simd_mac16_4);
}
void test_simd_muls32()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_muls32);
}
void test_simd_mac32_4()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 c[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg32 dst = {0};

    GENERATE_2_OP_INIT_DST_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, c, opt1, opt2, dst, simd_mac32_4);
}
void test_simd_fshift()
{
    Reg32 b[63] = {0};

    Reg32 start;
    start.word = -31;

    size_t b_size = sizeof(b) / sizeof(U32);

    gen_array(b, b_size, start, 1);

    Reg128 opt1 = {0};
    Reg32 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, f_a, b, opt1, opt2, dst, simd_fshift);
}
void test_simd_frelu()
{
    Reg128 opt1 = {0};
    Reg128 dst = {0};

    GENERATE_1_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, f_a, opt1, dst, simd_frelu);
}
void test_simd_fleaky()
{
    Reg128 opt1 = {0};
    Reg128 dst = {0};

    GENERATE_1_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, f_a, opt1, dst, simd_fleaky);
}

void test_simd_relu()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[1] = {0};

    Reg128 opt1 = {0};
    Reg32 opt2 = {0};
    Reg64 dst = {0};

    Reg32 start;
    start.word = 14;

    size_t b_size = sizeof(b) / sizeof(U32);

    gen_array(b, b_size, start, 1);

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_relu);
}
void test_simd_leaky()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[1] = {0};

    Reg128 opt1 = {0};
    Reg32 opt2 = {0};
    Reg64 dst = {0};

    Reg32 start;
    start.word = 15;

    size_t b_size = sizeof(b) / sizeof(U32);

    gen_array(b, b_size, start, 1);

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_leaky);
}
void test_simd_linear()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[1] = {0};

    Reg128 opt1 = {0};
    Reg32 opt2 = {0};
    Reg64 dst = {0};

    Reg32 start;
    start.word = 15;

    size_t b_size = sizeof(b) / sizeof(U32);

    gen_array(b, b_size, start, 1);

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_linear);
}

// new add
void test_simd_sample()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[2] = {0, 1};

    Reg128 opt1 = {0};
    Reg32 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_sample);
}
void test_simd_sl()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[17] = {0};

    Reg128 opt1 = {0};
    Reg32 opt2 = {0};
    Reg128 dst = {0};

    Reg32 start;
    start.word = -8;

    size_t b_size = sizeof(b) / sizeof(U32);

    gen_array(b, b_size, start, 1);

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_sl);
}
void test_simd_xor()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_xor);
}
void test_simd_and()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_and);
}
void test_simd_or()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_or);
}
void test_simd_2bit_to_1bit()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_2bit_to_1bit);
}
void test_simd_1bit_to_2bit()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg64 opt1 = {0};
    Reg128 dst = {0};

    GENERATE_1_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, opt1, dst, simd_1bit_to_2bit);
}
void test_simd_add32()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_add32);
}
void test_simd_sub32()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_sub32);
}
void test_simd_add16()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_add16);
}
void test_simd_sub8()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_sub8);
}
void test_simd_max16()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_max16);
}
void test_simd_min16()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_min16);
}
void test_simd_max16_mak()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_max16_mak);
}
void test_simd_max8()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_max8);
}
void test_simd_min8()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};
    Reg32 b[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 opt2 = {0};
    Reg128 dst = {0};

    GENERATE_2_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, b, opt1, opt2, dst, simd_min8);
}
void test_simd_shuffle64()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg64 opt1 = {0};
    Reg64 dst = {0};

    GENERATE_1_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, opt1, dst, simd_shuffle64);
}
void test_simd_shuffle128()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg128 dst = {0};

    GENERATE_1_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, opt1, dst, simd_shuffle128);
}
void test_simd_max16_8()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg32 dst = {0};

    GENERATE_1_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, opt1, dst, simd_max16_8);
}
void test_simd_min16_8()
{
    Reg32 a[] = {0x7fffffff, 0x80000000, 0x00000000, 0x5a5a5a5a, 0xa5a5a5a5};

    Reg128 opt1 = {0};
    Reg32 dst = {0};

    GENERATE_1_OP_CODE(simd_mem_upasm_file, simd_upinc_file, simd_upasm_file, a, opt1, dst, simd_min16_8);
}
void test_simd_min_disp()
{
}
void test_simd_interp()
{
}
void pc_simd_instruction_test()
{
    creat_u31_project("u31_simd_test", simd_code_file);
    simd_mem_upasm_file = simd_code_file.mem_upasm_file;
    simd_upinc_file = simd_code_file.upinc_file;
    simd_upasm_file = simd_code_file.upasm_file;

    gen_mem_upasm_diff_buffer_lable(simd_mem_upasm_file, 16);
    gen_upinc_diff_buffer_lable(simd_upinc_file);
    gen_upasm_head_code(simd_upasm_file);

    // test_simd_sl();
    // test_simd_xor();
    // test_simd_and();
    // test_simd_or();
    // test_simd_2bit_to_1bit();
    // test_simd_1bit_to_2bit();
    // test_simd_add32();
    // test_simd_sub32();
    // test_simd_add16();
    // test_simd_sub8();
    // test_simd_max16();
    // test_simd_min16();
    // test_simd_max16_mak();
    // test_simd_max8();
    // test_simd_min8();
    // test_simd_shuffle64();
    // test_simd_shuffle128();
    // test_simd_max16_8();
    // test_simd_min16_8();
    // test_simd_match8();
    // test_simd_unpack8();
    // test_simd_unpack16();
    // test_simd_add8_ext1();
    // test_simd_sub8_ext1();
    // test_simd_add8_ext2();
    // test_simd_sub8_ext2();
    // test_simd_add16_ext1();
    // test_simd_sub16_ext1();
    // test_simd_add16_ext2();
    // test_simd_sub16_ext2();
    // test_simd_mask8();
    // test_simd_mask16();
    // test_simd_match16();
    // test_simd_8to16();
    // test_simd_8to32();
    // test_simd_16to32();
    // test_simd_sub16();
    // test_simd_shift32();
    // test_simd_shift16();
    // test_simd_add8();
    // test_simd_add8_16();
    // test_simd_max32();
    // test_simd_min32();
    // test_simd_max32_mak();
    // test_simd_min32_mak();
    // test_simd_min16_mak();
    // test_simd_max8_mak();
    // test_simd_min8_mak();
    // test_simd_enlarg8();
    // test_simd_enlarg16();
    // test_simd_enlarg32();
    // test_simd_ext32();
    // test_simd_set();
    // test_simd_match();
    // test_simd_fmax1();
    // test_simd_fmin1();
    // test_simd_fmax4();
    // test_simd_fmin4();
    // test_simd_fabs();
    // test_simd_fadd();
    // test_simd_fsub();
    // test_simd_fmul();
    // test_simd_16to8();
    // test_simd_32to16();
    // test_simd_i8f32();
    // test_simd_i32f32();
    // test_simd_f32i32();
    // test_simd_f32i64();
    // test_simd_mul();
    // test_simd_mac16_8();
    // test_simd_fshift();
    // test_simd_muls32(); 
    // test_simd_mac32_4(); 
    // test_simd_muls16();
    // test_simd_mac16_4();
    // test_simd_frelu();
    // test_simd_fleaky();
    // test_simd_relu();
    // test_simd_leaky();
    // test_simd_linear();
    // test_simd_shuffle8(); // 自动生成的U31代码需要修改, 操作数2的循环次数改为40和间隔改为8
    // test_simd_sample();   // 自动生成的U31代码需要修改, 操作数2只支持立即数,需修改代码
    /**
        ifu r13 == 0 {
            simd_sample U31_Result_128bit, r73, 0
        }
        ifu r13 == 1 {
            simd_sample U31_Result_128bit, r73, 1
        }
    */
    // test_simd_ext8(); // 自动生成的U31代码需要修改, 操作数2只支持立即数,需修改代码
    /**
        ifu r13 == 0 {
            simd_ext8 U31_Result_128bit, r12, 0
        }
        ifu r13 == 1 {
            simd_ext8 U31_Result_128bit, r12, 1
        }
    */
    // test_simd_ext16();  // 自动生成的U31代码需要修改, 操作数2只支持立即数,需修改代码
    /**
        ifu r13 == 0 {
            simd_ext16 U31_Result_128bit, r12, 0
        }
        ifu r13 == 1 {
            simd_ext16 U31_Result_128bit, r12, 1
        }
    */
    // test_simd_fsum();    // not pass
    // test_simd_fmac_4(); // not pass
    // test_simd_min_disp();   // 未完成
    // test_simd_interp();     // 未完成
    gen_upasm_tail_code(simd_upasm_file);

    close_project(simd_code_file);
}
